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MX26C512A
512K-BIT [64K x 8] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
FEATURES
* * * * * * *
64K x 8 organization +5V operating power supply +12.75V program/erase voltage Electric erase instead of UV light erase Fast access time: 70/90/100/120/150 ns Totally static operation Completely TTL compatible
* * * *
Operating current: 30mA Standby current: 100uA 100 minimum erase/program cycles Package type: - 28 pin plastic DIP - 28 pin SOP GY OLO - 32 pin PLCC HN - 28 pin TSOP(I) TEC
GENERAL DESCRIPTION
The MX26C512A is a 12.75V/5V, 512K-bit, MTP EPROMTM (Multiple Time Programmable Read Only Memory). It is organized as 64K words by 8 bits per word, operates from a + 5 volt supply, has a static standby mode, and features fast single address location programming. It is designed to be reprogrammed and erased by an EPROM programmer or on-board. All programming/ erasing signals are TTL levels, requiring a single pulse.
ENT PAT
ED
The MX26C512A supports an intelligent quick pulse programming algorithm which can result in a programming time of less than 30 seconds. This MTP EPROMTM is packaged in industry standard 28 pin dual-in-line packages, 32 pin PLCC packages or 28 pin TSOP packages and 28 pin SOP packages.
PIN CONFIGURATIONS
PDIP/SOP
A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A14 A13 A8 A9 A11 OE/VPP A10 CE Q7 Q6 Q5 Q4 Q3
BLOCK DIAGRAM
PLCC
VCC A12 A15 A14 A13 NC A7 4 1 32 30 29
CE OE
CONTROL LOGIC
OUTPUT BUFFERS
Q0~Q7
A6 A5 A4 A3 A2 A1 A0 NC Q0
5
A8 A9 A11 NC
MX26C512A
9
MX26C512A
25
OE/VPP A10 CE Q7
A0~A15 ADDRESS INPUTS
. . . . . . . .
Y-DECODER
X-DECODER
. . . . . . . .
Y-SELECT
512K BIT CELL MAXTRIX
13 14 Q1 Q2 GND
17 Q3 Q4 NC
21 20 Q5
Q6
VCC GND
VPP
TSOP
OE/VPP A11 A9 A8 A13 A14 VCC A15 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 CE Q7 Q6 Q5 Q4 Q3 GND Q2 Q1 Q0 A0 A1 A2
PIN DESCRIPTION
SYMBOL A0~A15 Q0~Q7 CE OE VPP NC VCC GND PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Program Supply Voltage No Internal Connection Power Supply Pin (+5V) Ground Pin
REV.1.8, JUL. 13 , 1998
MX26C512A
P/N: PM0455
Patent#: US#5,523,307
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MX26C512A
FUNCTIONAL DESCRIPTION
When the MX26C512A is delivered, or it is erased, the chip has all 512K bits in the "ONE", or HIGH state. "ZEROs" are loaded into the MX26C512 through the procedure of programming. ERASE MODE The MX26C512A is erased by EPROM programmer or in-system. The device is set up in erase mode when A9 =OE/VPP = 12.75V are applied, with VCC = 5V. (Algorithm is shown in Figure 3). The erase time is around 1sec. If the erase is not verified, an additional erase processes will be repeated for a maximum of 200 times.
PROGRAMMING MODE
PROGRAMMMING ALGORITHM
PROGRAM INHIBIT MODE The MX26C512A is programmed by an EPROM programmer or on-board. The device is set up in the programming mode when the programming voltage OE/ VPP = 12.75V is applied, with VCC = 5 V (Algorithm shown in Figure 1). Programming is achieved by applying a single TTL low level 25us pulse to the CE input after addresses and data lines are stable. If the data is not verified, additional pulses are applied for a maximum of 20 pulses. After the data is verified, one 25us pulse is applied to overprogram the byte so that program margin is assured. This process is repeated while sequencing through each address of the device. When programming is completed, the data at all the addresses are verified at VCC = 5V 10%. The VCC supply of the MXIC On-Board Programming Algorithm is designed to be 5V 10% particularly to facilitate the programming operation under the on-board application environment. But it can also be implemented in an industrial-standard EPROM programmer. Programming of multiple MX26C512A in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE and OE, all like inputs of the parallel MX26C512 may be common. A TTL low-level program pulse applied to an MX26C512A CE input with OE/VPP = 12.75 0.25 V will program that MX26C512A. A high-level CE input inhibits the other MX26C512A from being programmed.
PROGRAM VERIFY MODE Verification should be performed on the programmed bits to determine that they were correctly programmed. The verification should be performed with OE/VPP and CE, at VIL. Data should be verified tDV after the falling edge of CE.
ERASE VERIFY MODE
COMPATIBILITY WITH MX27C512 FAST PROGRAMMING ALGORITHM
Besides the On-Board Programming Algorithm, the Fast Programming Algorithm of MX27C512 also applies to MX26C512A. MXIC Fast Algorithm is the conventional EPROM programing algorithm and is available in industrial-standard EPROM programmers. A user of industrial-standard EPROM programmer can choose either of the algorithms base on his preference. The device is set up in the fast programming mode when the programming voltage OE/VPP = 12.75V isapplied, with VCC = 6.25V, (Algorithm is shown in Figure 2). The programming is achieved by appling a single TTL low level 25~100us pulse to the CE input after addresses and data line are stable. If the data is not verified, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the device. When the programming mode is completed, the data in all address is verified at VCC = 5V 10%.
P/N: PM0455 Patent#: US#5,523,307
Verification should be performed on the erased chip to determine that whole chip(all bits) was correctly erased. Verification should be performed with OE/VPP and CE at VIL and VCC = 5V.
AUTO IDENTIFY MODE The auto identify mode allows the reading out of a binary code from a MTP that will identify its manufacturer and device type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25 5C ambient temperature range C that is required when programming the MX26C512A. To activate this mode, the programming equipment must force 12.75V on address line A9 of the device. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All
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MX26C512A
other address lines must be held at VIL during auto identify mode. Byte 0 ( A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the MX26C512A, these two identifier bytes are given in the Mode Select Table. All identifiers for the manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. memory device. SYSTEM CONSIDERATIONS During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 uF bulk electrolytic capacitor should be used between VCC and GND for each of the eight devices. The location of the capacitor should be close to where the power supply is connected to the array.
READ MODE The MX26C512A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tACC - tOE.
STANDBY MODE The MX26C512A has a CMOS standby mode which reduces the maximum VCC current to 100 uA. It is placed in CMOS standby when CE is at VCC 0.3 V. The MX26C512A also has a TTL-standby mode which reduces the maximum VCC current to 1.5 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input.
TWO-LINE OUTPUT CONTROL FUNCTION To accommodate multiple memory connections, a twoline control function is provided to allow for: 1. Low memory power dissipation, 2. Assurance that output bus contention will not occur. It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular
P/N: PM0455
Patent#: US#5,523,307
REV.1.8, JUL. 13 , 1998
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INDEX
MX26C512A
MODE SELECT TABLE
PINS MODE Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Erase Erase Verify Program Inhibit Manufacturer Code Device Code(26C512) CE VIL VIL VIH VCC VIL VIL VIL VIL VIH VIL VIL OE/VPP VIL VIH X X VPP VIL VPP VIL X VIL VIL A0 X X X X X X X X X VIL VIH A9 X X X X X X VPP X X VH VH OUTPUTS DOUT High Z High Z High Z DIN DOUT HIGH Z DOUT High Z C2H D1H
NOTES: 1. VH = 12.0V 0.5V 2. X = Either VIH or VIL(For auto select)
3. A1 - A8 = A10 - A15 = VIL(For auto select) 4. See DC Programming Characteristics for VPP voltage during programming.
FIGURE 1. PROGRAMMING FLOW CHART
START
ADDRESS = FIRST LOCATION
VCC = 5V VPP = 12.75V X=0
PROGRAM ONE 25us PULSE
INTERACTIVE SECTION
INCREMENT X
YES X = 20 ?
NO FAIL VERIFY BYTE ?
PROGRAM ONE 25us PULSE PASS NO INCREMENT ADDRESS LAST ADDRESS FAIL YES PROGRAM ONE 25us PULSE
VCC = 5V
VERIFY SECTION
VPP = VIL
VERIFY ALL BYTES ? PASS DEVICE PASSED
FAIL
DEVICE FAILED
P/N: PM0455
Patent#: US#5,523,307
REV.1.8, JUL. 13 , 1998
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MX26C512A
FIGURE 2. COMPATIBILITY WITH MX27C512 FAST PROGRAMMING FLOW CHART
START
ADDRESS = FIRST LOCATION
VCC = 6.25V OE/VPP = 12.75V
PROGRAM ONE 25~100us PULSE
NO INCREMENT ADDRESS
LAST ADDRESS ?
YES
ADDRESS = FIRST LOCATION
INCREMENT ADDRESS NO
LAST ADDRESS ?
X=0
PASS
VERIFY BYTE
FAIL
INCREMENT X
YES NO
PROGRAM ONE 25~100us PULSE
X = 25 ?
VCC = 5.0V OE/VPP = VIL
YES
COMPARE ALL BYTES TO ORIGINAL DATA
FAIL
DEVICE FAILED
PASS
DEVICE PASSED
P/N: PM0455
Patent#: US#5,523,307
REV.1.8, JUL. 13 , 1998
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MX26C512A
FIGURE 3. ERASING MODE FLOW CHART
START
X=0
PROGRAM ALL "0"
A9 = 12.75V VCC = 5V VPP = 12.75V
CHIP ERASE (0.5s)
A9 = VIL or VIH VCC = 5V OE/VPP = VIL All Bits Verify FAIL ERASE VERIFY ? INCREMENT X X = 200 ? YES NO
PASS
CHIP ERASE (0.5s)
DEVICE FAILED
DEVICE PASSED
P/N: PM0455
Patent#: US#5,523,307
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MX26C512A
SWITCHING TEST CIRCUITS
DEVICE UNDER TEST
1.8K ohm +5V
CL 6.2K ohm
DIODES = IN3064 OR EQUIVALENT
CL = 100 pF including jig capacitance(30pF for 70 ns parts)
SWITCHING TEST WAVEFORMS
3.0V 1.5V 0V
TEST POINTS INPUT OUTPUT
1.5V
AC TESTING: (1) Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 10ns. (2) For MX26C512A
P/N: PM0455
Patent#: US#5,523,307
REV.1.8, JUL. 13 , 1998
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MX26C512A
ABSOLUTE MAXIMUM RATINGS
RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 & Vpp VALUE 0oC to 70oC -65oC to 125oC -0.5V to 7.0V -0.5V to VCC + 0.5V -0.5V to 7.0V -0.5V to 13.5V NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change.
DC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V 10%
SYMBOL VOH VOL VIH VIL ILI ILO ICC3 ICC2 ICC1 PARAMETER Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current VCC Power-Down Current VCC Standby Current VCC Active Current 2.0 -0.3 -10 -10 MIN. 2.4 0.4 VCC + 0.5 0.8 10 10 100 1.5 30 MAX. UNIT V V V V uA uA uA mA mA VIN = 0 to 5.5V VOUT = 0 to 5.5V CE = VCC 0.3V CE = VIH CE = VIL, f=5MHz, Iout = 0mA CONDITIONS IOH = -0.4mA IOL = 2.1mA
CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only)
SYMBOL CIN COUT CVPP PARAMETER Input Capacitance Output Capacitance VPP Capacitance TYP. 8 8 18 MAX. 8 12 25 UNIT pF pF pF CONDITIONS VIN = 0V VOUT = 0V VPP = 0V
P/N: PM0455
Patent#: US#5,523,307
REV.1.8, JUL. 13 , 1998
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INDEX
MX26C512A
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V 10%
26C512A -70 SYMBOL tACC tCE tOE tDF tOH PARAMETER Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay OE High to Output Float, or CE High to Output Float Output Hold from Address, CE or OE which ever occurred firs MIN. MAX. 70 70 35 20 MIN. 26C512A -90 MAX. 90 90 40 25 UNIT ns ns ns ns ns CONDITIONS CE = OE = VIL OE = VIL CE = VIL
0 0
0 0
26C512A -10 SYMBOL tACC tCE tOE tDF tOH PARAMETER Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay OE High to Output Float, MIN. MAX. 100 100 45 30
26C512A -12 MIN. MAX. 120 120 50 35
26C512A -15 MIN. MAX. 150 150 65 50 UNIT ns ns ns ns ns CONDITIONS CE = OE = VIL OE = VIL CE = VIL
0
0 0
0 0
or CE High to Output Float Output Hold from Address, 0 CE or OE which ever occurred first
DC PROGRAMMING CHARACTERISTICS TA = 25oC 5oC
SYMBOL VOH VOL VIH VIL ILI VH ICC3 IPP2 PARAMETER Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current A9 Auto Select Voltage VCC Supply Current (Program/Erase & Verify) VPP Supply Current(Program)/Erase 2.0 -0.3 -10 11.5 MIN. 2.4 0.4 VCC + 0.5 0.8 10 12.5 50 50 MAX. UNIT V V V V uA V mA mA CE = PGM = VIL, OE = VIH VCC2 VPP2 IPP A9 Programming & Erase Supply Voltage Programming & Erase Voltage A9 Auto Select Current /Erase 4.5 12.5 6.5 13.0 1 V V mA CE = PGM = VIL, OE = VIH VIN = 0 to 5.5V CONDITIONS IOH = -0.40mA IOL = 2.1mA
P/N: PM0455
Patent#: US#5,523,307
REV.1.8, JUL. 13 , 1998
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MX26C512A
AC PROGRAMMING CHARACTERISTICS TA = 25oC 5oC
SYMBOL tAS tOES tDS tAH tDH tDFP tVPS tPW tVCS tDV tCES tOE tER tEW tEV tPV tA9S tPVS tEVS PARAMETER Address Setup Time OE Setup Time Data Setup Time Address Hold Time Data Hold Time CE to Output Float Delay VPP Setup Time Program Pulse Width VCC Setup Time Data Valid from CE CE Setup Time Data valid from OE Erase Recovery Time Erase Pulse Width Erase Verify Time Program Verify Time A9 Setup Time Program Verify Setup Erase Verify Setup 2.0 2 0.5 0.5 0.5 200 200 2.0 150 MIN. 2.0 2.0 2.0 0 2.0 0 2.0 20 2.0 250 105 130 MAX. UNIT us us us us us ns us us us ns us ns s s ns ns us us s CONDITIONS
WAVEFORMS
READ CYCLE
ADDRESS INPUTS
tACC
DATA ADDRESS
CE
tCE
OE
tDF
DATA OUT
tOE
VALID DATA
tDH
P/N: PM0455
Patent#: US#5,523,307
REV.1.8, JUL. 13 , 1998
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MX26C512A
PROGRAMMING WAVEFORMS
PROGRAM VIH
PROGRAM VERIFY
Addresses
VIL tAS
DATA
tDFP tDS VPP1 tDH tDV
OE/VPP
VIL tPRT tVPS VIH tPR tPW tPVS tAH
CE
VIL tVCS VCC1 tPV
VCC
VCC
ERASE WAVEFORMS
ERASE
VPP A9
ERASE VERIFY
ADDRESS
VIH
OTHERS NOT CARE
VIL
OUT
tEVS VPP
OUT
OE/VPP
VIL VIH tVPS tEV
CE
VIL tCES tEW tER
P/N: PM0455
Patent#: US#5,523,307
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INDEX
MX26C512A
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO. MX26C512APC-70 ACCESS TIME(ns) 70 OPERATING CURRENT MAX.(mA) 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 STANDBY CURRENT MAX.(uA) 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 PACKAGE 28 Pin DIP 28 Pin SOP 32 Pin PLCC 28 Pin TSOP(I) 28 Pin DIP 28 Pin SOP 32 Pin PLCC 28 Pin TSOP(I) 28 Pin DIP 28 Pin SOP 32 Pin PLCC 28 Pin TSOP(I) 28 Pin DIP 28 Pin SOP 32 Pin PLCC 28 Pin TSOP(I) 28 Pin DIP 28 Pin SOP 32 Pin PLCC 28 Pin TSOP(I)
MX26C512AMC-70 70 MX26C512AQC-70 70 MX26C512ATC-70 MX26C512APC-90 70 90
MX26C512AMC-90 90 MX26C512AQC-90 90 MX26C512ATC-90 MX26C512APC-10 90 100
MX26C512AMC-10 100 MX26C512AQC-10 100 MX26C512ATC-10 MX26C512APC-12 100 120
MX26C512AMC-12 120 MX26C512AQC-12 120 MX26C512ATC-12 MX26C512APC-15 120 150
MX26C512AMC-15 150 MX26C512AQC-15 150 MX26C512AC-15 150
P/N: PM0455
Patent#: US#5,523,307
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MX26C512A
PACKAGE INFORMATION
28-PIN PLASTIC DIP (600 mil)
ITEM A B C D E F G H I J K L M
NOTE:
MILLIMETERS 37.34 max 2.03 [REF] 2.54 [TP] .46 [Typ.] 32.99 1.52 [Typ.] 3.30 .25 .51 [REF] 3.94 .25 5.33 max. 15.22 .25 13.84 .25 .25 [Typ.]
INCHES 1.470 max .080 [REF] .100 [TP] .018 [Typ.] 1.300 .060 [Typ.] .130 .010 .020 [REF] .155 .010 .210 max. .600 .010 .545 .010 .010 [Typ.]
28
15
1 A
14 K L
I H F D E
J G
Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition.
C
B
M
0~15
32-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
A
ITEM A B C D E F G H I J K L M N
NOTE:
MILLIMETERS 12.44 .13 11.50 .13 14.04 .13 14.98 .13 1.93 3.30 .25 2.03 .13 .51 .13 1.27 [Typ.] .71[REF] .46 [REF] 10.40/12.94 (W) (L) .89 R .25 (TYP.)
INCHES .490 .005 .453 .005 .553 .005 .590 .005 .076 .130 .010 .080 .005 .020 .005 .050 [Typ.] .028[REF] .018 [REF] .410/.510 (W) (L) .035 R .010 (TYP.)
F G 13 14 9 5 4
B 1
32
30 29
25
C
D
21 20 E N
17
Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition.
H I K L M J
P/N: PM0455
Patent#: US#5,523,307
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MX26C512A
28-PIN PLASTIC TSOP
ITEM A B C D F H I J K L M N
MILLIMETERS 13.4 .2 11.8 .1 8.0 .1 .15 .01 .2 .03 .55 [Typ.] .425 [Typ.] .05 [Min.] 1.00 .05 1.25 [Max.] .05 .20 O ~ 5
A B
C
N M
K D E F G H I J
L
NOTE: Each lead centerline is located within .25 mm of its true position [TP] at maximum material condition.
28-PIN PLASTIC SOP(330 mil)
ITEM A B C D E F G H I J K L
NOTE:
MILLIMETERS 18.62 max. 1.194 max 1.27 [TP] .41 [Typ.] .10 min. 2.85 max. 2.49 .13 11.81 .31 8.41 .13 1.70 .20 .25 [Typ.] .91 .20
INCHES .733 max. .047 max .050 [TP] .016 [Typ.] .004 min. .110 max. .098 .005 .465 .012 .331 .005 .067 .008 .010 [Typ.] .036 .008
28
15
1 A
14
H I G F K J
Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition.
D
C
B
E L
P/N: PM0455
Patent#: US#5,523,307
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MX26C512A
Revision History
Revision# 1.2 1.3 1.4 Description Add 28 pin TSOP and SOP packages. Erasing mode flow chart: Chip erase (5s)----> (1s). Programming waveforms: CE changed. MTP ROM--->MTP EPROM Chip erase(1s)--->0.5s. X = 60?--->200? Switching Test Waveforms revise. tEW Erase Pulse Width 1 sec---> 0.5 sec. Programming/erase waveforms modifiction. VPP:from 12.0~13V to 12.5V ~13V. Erase Verify Time: 60 ---->200. Change Part Name: 26C512 ---> 26C512A Change tPW:Min. 95us -->Min. 20us. Programming flow chart revised. Mode Select Table, Erase Mode A9=VH-->A9=Vpp. Erase flow chart revised. Delete IPP in DC CHARACTERISTICS Date 3/28/1997 4/10/1997 5/30/1997
1.5 1.6 1.7
7/25/1997 11/05/1997 2/10/1998
1.8
7/13/1998
P/N: PM0455
Patent#: US#5,523,307
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MX26C512A
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-8888 FAX:+886-3-578-8887
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http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
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